In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development.
Online VLSI Verification Course starts with a good overview of functional verification methodologies and SystemVerilog language and then it explains the nuts and bolts of building class-based verification environment using SystemVerilog HDVL in detail. As part of SystemVerilog for Verification module it trains you extensively on creating the test benches using OOP, constraint random simulation and verification sign-off using functional coverage. Finally, it also walks you through UVM methodology concepts and explains the need of using IEEE standard methodologies like UVM to create SystemVerilog based test benches.
USP : This course is very different from the standard textbooks and training courses available in the market. This verification course is completely based on a standard test bench architecture which can be used for creating SystemVerilog test benches and at the same they can be easily migrated to UVM framework. Also, we use two main examples throughout the course to explain all the methodology and language concepts. One is a small dual port RAM RTL design which is used for explaining all the language concepts in detail, especially for the testbench implementation. The other one is a complex SOC design which is used for explaining the use-cases of certain SystemVerilog language features and challenges of migrating IP level testbenches to SOC level testbenches.
Any electronics engineer with a good knowledge in RTL design using Verilog HDL can learn all the verification methodologies and SystemVerilog language concepts from this course and grow as a hand-on verification expert.
we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certification.
The universal verification methodology- (UVM-) based functional verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional verification environment files and model map files are described.
The framework is developed both with host interface and with core using virtual register interface (VRI) approach. This modeling and functional verification framework is used in real-time image signal processing applications including cell phone, smart cameras, and image compression.
